1. Field of the Invention
The present invention relates to a semiconductor device, more specifically, to a minute semiconductor device requiring high-grade characteristics of a gate insulating film therein and a method of fabricating the same.
2. Description of the Related Art
A memory cell comprised of a so-called metal oxide nitride oxide semiconductor (hereinafter referred to as “MONOS”: metal—silicon oxide film—silicon nitride film—silicon oxide film—semiconductor) is known as one type of electrically writable and erasable non-volatile semiconductor memory devices, which stores data by trapping electric charges inside a silicon nitride film. A MONOS memory is capable of writing and erasing operations with relatively low voltage compared with a floating-gate memory. In addition, the MONOS memory cell comprised of a single layer gate structure has a smaller aspect ratio of a gate in comparison with the floating-gate memory cell that requires a multilayer gate structure. Therefore, the MONOS memory cell has an advantage that it is suitable for miniaturizing of elements therein.
A cross section of a conventional MONOS memory cell prepared by local oxidation (LOCOS) isolation is illustrated in FIG. 94.
In FIG. 94, a tunnel insulating film 101 of a memory cell is formed on a semiconductor substrate 100, and an element isolation region 102 with a film thickness greater than that of the tunnel insulating film 101 is formed so as to sandwich the tunnel insulating film 101. On the surfaces of the element isolation region 102 and the tunnel insulating film 101, formed is a charge storing layer 103 made of a silicon nitride film. A barrier insulating film 104 is formed on the charge storing layer 103. Furthermore, a gate electrode 105 is formed on the barrier insulating film 104.
Incidentally, shallow trench isolation (STI) is becoming an important technology instead of the conventional LOCOS isolation as miniaturizing progresses. In particular, as an element isolation method suitable for floating-gate non-volatile memories, self-aligned STI is proposed (“A 0.67 μm2 SELF-ALIGNED SHALLOW TRENCH ISOLATION CELL (SA-STI CELL) FOR 3V-only 256 Mbit NAND EEPROMs” IEDM Tech. Dig. 1994 pp 61–64). There, a gate insulating film formed under a floating gate is made in a thickness greater than other parts at an edge of a gate electrode. In the self-aligned STI, by forming element isolation trenches by self-alignment with respect to the floating gate, which is a charge storing layer, concentration of electric fields at the element isolation trenches attributable to penetrating of a part of the gate electrode into the element isolation edge is prevented. As a result, unevenness of cell characteristics can be improved whereby high reliability is achieved.
In FIG. 1 and FIG. 3(a) among others in Japanese Patent Publication No. 4-12573, disclosed is a structure of a MONOS non-volatile semiconductor memory device arranged to allow a gate insulating film in a region of an interface with a surrounding selective oxide film to reside entirely inside a trench in order to prevent a sidewalk phenomenon.
It should be further noted that FIG. 4 among others in Japanese Patent Publication No. 11-330277 discloses the fact that a non-volatile memory using an insulating film as a charge storing layer as in MONOS shows inferior read-disturb characteristics.
The following problems arise in the above-described conventional semiconductor device.
An oxide film is formed thick at an element isolation edge 106 attributable to an influence by thermal oxidation for forming an element isolation region, which results in deterioration of write operation and erase operation characteristics in that region. In other words, since the thickness of the insulating film grows large at the element isolation edge, electric fields thereabout are weakened and thresholds are thereby lowered.
Since electric charges are trapped in the silicon nitride film which is the insulating film in the MONOS structure, carriers do not move within the charge storing layer. For this reason, when a write pulse is supplied, only a channel edge is left low in a threshold. Such phenomenon is observed as a subthreshold leakage or a hump with respect to transistor characteristics. The phenomenon referred to as sidewalk is problematic in the MONOS memory cell because the phenomenon narrows a writing/erasing window thereof.
According to the above-mentioned Japanese Patent Publication No. 4-12573, a trench is provided in a semiconductor substrate and an insulating film is provided inside the trench. However, the thickness of the film is larger near an element isolation region thereof. Accordingly, control characteristics are deteriorated due to occurrence of concentration of electric fields thereabout.